R/W

Bit 0

1

Bit 1

1

Bit 2

0

Bit 3

0

Bit 4

0

Bit 5

1

Bit 7

1

Bit 6

MSB

LSB

I

2

C Slave Address (chip address)

start

msb Chip Address lsb

w

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

ack from slave

ack from slave

SCL

SDA

start

Id = 63h

w

ack

addr = 0Ah

ack

ack

Data = 03h

stop

22

LM3644, LM3644TT

SNVSA52E – AUGUST 2014 – REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: LM3644 LM3644TT

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Copyright © 2014–2016, Texas Instruments Incorporated

Figure 39. Write Cycle W = Write (SDA = "0") R = Read (SDA = "1") Ack = Acknowledge

(SDA Pulled Down by Either Master or Slave) ID = Chip Address, 63h for LM3644

8.5.2.4 I2C-Compatible Chip Address

The device address for the LM3644 is 1100011 (0x63). After the START condition, the I2C-compatible master

sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE and R/W = 1

indicates a READ. The second byte following the device address selects the register address to which the data is

written. The third byte contains the data for the selected register.

Figure 40. I2C-Compatible Chip Address

8.6 Register Descriptions

REGISTER NAME

INTERNAL HEX ADDRESS

POWER ON/RESET VALUE

LM3644

Enable Register

0x01

0x80

IVFM Register

0x02

0x01

LED1 Flash Brightness Register

0x03

0xBF

LED2 Flash Brightness Register

0x04

0x3F

LED1 Torch Brightness Register

0x05

0xBF

LED2 Torch Brightness Register

0x06

0x3F

Boost Configuration Register

0x07

0x09

Timing Configuration Register

0x08

0x1A

TEMP Register

0x09

0x08

Flags1 Register

0x0A

0x00

Flags2 Register

0x0B

0x00

Device ID Register

0x0C

0x02 or 0x04 for LM3644TT

Last Flash Register

0x0D

0x00