MP86933

– 16V, INTELLI-PHASE SOLUTION IN TQFN 3X3 PACKAGE

MP86933 Rev.1.2

www.MonolithicPower.com

12

5/26/2021

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APPLICATION INFORMATION

PCB Layout Guidelines

Efficient

PCB

layout

is

critical

for

stable

operation. For best performance, refer to Figure

4 and follow the guidelines below.

1. Place the input MLCC capacitors as close to

VIN and PGND as possible.

2. Place the major MLCC capacitors on the

same layer as the MP86933.

3. Maximize the VIN and PGND copper plane

to minimize the parasitic impedance.

4. Place as many PGND vias as possible close

to

PGND

to

minimize

both

parasitic

impedance and thermal resistance.

5. Place the VCC decoupling capacitor close to

the device.

6. Connect AGND and PGND at the point of the

VCC capacitor's ground connection.

7. Place the BST capacitor as close to BST and

SW as possible.

8. Route the path with trace widths 20 mils or

higher.

9. Use 0.1µF to 1µF bootstrap capacitors.

10. Keep the CS signal trace away from high-

current paths like SW and PWM.

CBST

CVCC

CIN

L

SW

PGND

VIN

VOUT

1

2

7

8

9

10

11

13 12

3

6

5

4

PGND

VIN

SW

VIN

SW

PGND

Figure 4: Example of PCB Layout (Placement & Top Layer PCB)

Input Capacitor: 0805 & 0402 package

Inductor: 6.5 x 6.5 (mm)

VCC/BST capacitor: 0402 package

Via size: 20/10 mils