CC1010-RTY1 datasheet(71/150 Pages) TI2

71 / 150 page

CC1010

SWRS047A

Page 71 of 146

16.8 SPI Master

The SPI master interface allows

CC1010 to

communicate with peripheral devices such

as an external serial EEPROM interface. It

has a programmable data rate up to 3

MHz, depending on the frequency of the

main crystal.

The SPI master interface is controlled

using the SPCR register shown below.

Setting

SPCR.SPE

enables

the

SPI

interface. Pins P0.0, P0.1 and P0.2 are

then reconfigured as the serial clock

output SCK, the serial data output pin MO

and the serial data input pin MI. The

direction

bits

set

P0DIR(0)

and

P0DIR(2)

are then ignored, setting SCK

as an output and MI as an input. The

direction bit P0DIR(1) still determines the

direction of the master data output pin MO.

This

allows

the

SPI

master

communicate with a bi-directional data

line. P0DIR(1) should then be cleared

when transmitting and set when receiving

data, with MO and MI connected together

externally.

For

normal

full-duplex

operation of the SPI master, P0DIR(1)

must be cleared to set MO as an output.

Any other general purpose I/O-pin may be

used for slave select signals to the

peripheral modules.

CC1010-RTY1 데이터시트(PDF) 71 Page - Texas Instruments

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