CC1010-RTY1 datasheet(110/150 Pages) TI2

110 / 150 page

CC1010

SWRS047A

Page 110 of 146

17.13 Lock Indication

The frequency synthesis PLL has a lock

indicator, which can be read from the

LOCK

sample of the phase difference between

the reference frequency and the divided

VCO frequency. This bit gives a lock

accuracy of > 25 %, depending on the

division ratio set by the FREQ registers. To

be used as a lock indicator, this bit must

be sampled over a period of time to

increase the accuracy.

Otherwise LOCK_CONTINUOUS should be

used.

filtered

version

LOCK_INSTANT

, giving a lock accuracy of

99.3

with

PLL_LOCK_ACCURACY

cleared.

If lock is not achieved, the PLL should be

recalibrated as described on page 113.

LOCK (0xE4) - PLL Lock Register

Bit

Name

R/W

Reset value

Description

7:4

Reserved, read as 0

PLL_LOCK_ACCURACY

R/W

0 : Sets Lock Threshold = 127, Reset Lock

Threshold = 111 for continuous lock.

Corresponds to a worst case accuracy of

99.3%

1 : Sets Lock Threshold = 31, Reset Lock

Threshold =15 for continuous lock.

Corresponds to a worst case accuracy of

97.2%

PLL_LOCK_LENGTH

R/W

0 : Normal PLL lock window

1 : Not used

LOCK_INSTANT

None

Status bit from Lock Detector. The result of

one sample of the lock window on the PLL

reference clock

LOCK_CONTINUOUS

None

Status bit from Lock Detector, set according

to the PLL_LOCK_ACCURACY setting

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