전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

CD54HC86F 데이터시트(PDF) 11 Page - Texas Instruments

부품명 CD54HC86F
상세설명  CDx4HC86 Quadruple 2-Input XOR Gates
PDF  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

CD54HC86F 데이터시트(HTML) 11 Page - Texas Instruments

Back Button CD54HC86F Datasheet HTML 7Page - Texas Instruments CD54HC86F Datasheet HTML 8Page - Texas Instruments CD54HC86F Datasheet HTML 9Page - Texas Instruments CD54HC86F Datasheet HTML 10Page - Texas Instruments CD54HC86F Datasheet HTML 11Page - Texas Instruments CD54HC86F Datasheet HTML 12Page - Texas Instruments CD54HC86F Datasheet HTML 13Page - Texas Instruments CD54HC86F Datasheet HTML 14Page - Texas Instruments CD54HC86F Datasheet HTML 15Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 27 page
background image
The CD74HC86 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge rates
can cause oscillations and damaging shoot-through current. The recommended rates are defined in the Section
6.3.
Refer to the Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Section 6.5. Similarly, the ground voltage
is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as
specified by the VOL specification in the Section 6.5.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC86
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Section 6.1 is not violated. Most CMOS inputs have a resistive load measured in
megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Reference
Clock
Input Clock
Out
Figure 9-2. Typical application timing diagram
www.ti.com
CD74HC86, CD54HC86
SCHS137E – AUGUST 1997 – REVISED JUNE 2021
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: CD74HC86 CD54HC86



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com