7 Detailed Description

7.1 Overview

The ’HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to

LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the

ability to drive 10 LSTTL loads

These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on

the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.

This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric

limits.

The HCT logic family is functionally as well as pin compatible with the standard LS logic family

7.2 Functional Block Diagram

7.3 Device Functional Modes

Table 7-1. Truth Table(1)

INPUTS

OUTPUTS

R

CP

J

K

Q

Q

L

X

X

X

L

H

H

↓

L

L

No change

H

↓

H

L

H

L

H

↓

L

H

L

H

H

↓

H

H

Toggle

H

H

X

X

No change

(1)

H = high level (steady state), L = low level (steady state), X = irrelevant, ↓ = high-to-low transition

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CD54HC73, CD74HC73, CD74HCT73

SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022

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Product Folder Links: CD54HC73 CD74HC73 CD74HCT73