Performance Data: Output Skew, Jitter, Cross-Coupling, Noise Rejection (Spur Suppression),

Output Skew

Jitter Performance

CDCE706

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and Phase Noise

Skew is an important parameter for clock distribution circuits. It is defined as the time difference between outputs

that are driven by the same input clock. Table 5 shows the output skew (tsk(o)) of the CDCE706 for high-to-low

and low-to-high transitions over the entire range of supply voltages, operating temperature and output voltage

swing.

Table 5. Output Skew

PARAMETER

CONDITION

TYP

MAX

UNIT

VCCOUT = 2.5 V

130

250

ps

tsk(o)

Output skew

VCCOUT = 3.3 V

130

200

ps

Jitter is a major parameter for PLL-based clock driver circuits. This becomes important as speed increases and

timing budget decreases. The PLL and internal circuits of CDCE706 are designed for lowest jitter. The

peak-to-peak period jitter is only 60 ps (typical). Table 6 gives the peak-to-peak and rms deviation of

cycle-to-cycle jitter, period jitter and phase jitter as taken during characterization.

Table 6. Jitter Performance of CDCE706

TYP(1)

MAX(1)

PARAMETER

CONDITION

UNIT

rms

rms

Peak-Peak

Peak-Peak

(One Sigma)

(One Sigma)

fout = 50 MHz

55

–

75

–

tjit(cc)

Cycle-to-cycle jitter

fout = 133 MHz

50

–

85

–

ps

fout = 245.76 MHz

45

–

60

–

fout = 50 MHz

60

4

76

7

tjit(per)

Period jitter

fout = 133 MHz

55

5

84

11

ps

fout = 245.76 MHz

55

5

72

8

fout = 50 MHz

730

90

840

115

tjit(phase)

Phase jitter

fout = 133 MHz

930

130

1310

175

ps

fout = 245.76 MHz

720

90

930

125

(1)

All typical and maximum values are at VCC = 3.3 V, temperature = 25°C, VCCOUT = 3.3 V; one output is switching, data taken over

several 10,000 cycles.

Figure 26, Figure 27, and Figure 28 show the relationship between cycle-to-cycle jitter, period jitter, and phase

jitter over 10,000 samples. The jitter varies with a smaller or wider sample window. The cycle-to-cycle jitter and

period jitter show the measured value, whereas the phase jitter is the accumulated period jitter.

Cycle-to-Cycle jitter (tjit(cc)) is the variation in cycle time of a clock signal between adjacent cycles, over a random

sample of adjacent cycle pairs. Cycle-to-cycle jitter is never greater than the period jitter. It is also known as

adjacent-cycle jitter.

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