CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features

• Hysteresis on clock inputs for improved noise

immunity and increased input rise and fall times

• Asynchronous reset

• Complementary outputs

• Buffered inputs

• Typical fMAX = 60 MHz at VCC = 5 V,

CL = 15 pF, TA = 25℃

• Fanout (over temperature range)

– Standard outputs: 10 LSTTL loads

– Bus driver outputs: 15 LSTTL loads

• Wide operating temperature range: –55

℃ to 125℃

• Balanced propagation delay and transition times

• Significant power reduction compared to LSTTL

Logic ICs

• HC types

– 2 V to 6V operation

– High noise immunity: NIL = 30%, NIH = 30% of

VCC at VCC = 5 V

• HCT types

– 4.5 V to 5.5 V operation

– Direct LSTTL input logic compatibility,

VIL = 0.8 V (max), VIH = 2 V (min)

– CMOS input compatibility, II ≤ 1 μA at VOL, VOH

2 Description

The ’HC73 and CD74HCT73 utilize silicon gate

CMOS technology to achieve operating speeds

equivalent to LSTTL parts. They exhibit the low power

consumption of standard CMOS integrated circuits,

together with the ability to drive 10 LSTTL loads.

Package Information

PART NUMBER

PACKAGE

(1)

BODY SIZE (NOM)

CD74HC73M

SOIC (14)

8.65 mm × 3.90 mm

CD74HCT73M

SOIC (14)

8.65 mm × 3.90 mm

CD74HC73E

PDIP (14)

19.31 mm × 6.35 mm

CD74HCT73E

PDIP (14)

19.31 mm × 6.35 mm

CD54HC73F

CDIP (14)

19.55 mm × 6.71 mm

(1)

For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram

CD54HC73, CD74HC73, CD74HCT73

SCHS134G – FEBRUARY 1998 – REVISED OCTOBER 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.