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DLP2000AFQC.B 데이터시트(PDF) 27 Page - Texas Instruments |
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DLP2000AFQC.B 데이터시트(HTML) 27 Page - Texas Instruments |
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27 / 37 page ![]() Table 9-1. DMD Power-Down Sequence Requirements PARAMETER DESCRIPTION MIN MAX UNIT VBIAS Supply voltage level during power-down sequence 4.0 V VOFFSET Supply voltage level during power-down sequence 4.0 V VRESET Supply voltage level during power-down sequence –4.0 0.5 V www.ti.com DLP2000 DLPS140B – MARCH 2019 – REVISED MAY 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: DLP2000 |
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