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DLP4710LCFQL.B 데이터시트(PDF) 6 Page - Texas Instruments |
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DLP4710LCFQL.B 데이터시트(HTML) 6 Page - Texas Instruments |
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6 / 45 page ![]() Table 5-1. Pin Functions – Connector Pins (continued) PIN(1) TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET LENGTH(2) (mm) NAME NO. VSS B25 Ground Common return. Ground for all power. VSS B26 Ground VSS B29 Ground VSS B5 Ground VSS C25 Ground VSS C26 Ground VSS C27 Ground VSS C28 Ground VSS C5 Ground VSS D4 Ground VSS D5 Ground VSS D6 Ground VSS E25 Ground VSS F25 Ground VSS F26 Ground VSS F5 Ground VSS F6 Ground VSS G25 Ground VSS G26 Ground VSS H25 Ground VSS H4 Ground VSS H5 Ground VSS H6 Ground VSS J26 Ground VSS J4 Ground VSS K26 Ground VSS K4 Ground VSS K5 Ground VSS K6 Ground VSS L27 Ground (1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. (2) Net trace lengths inside the package: Relative dielectric constant for the FQL ceramic package is 9.8. Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns. Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm. (3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required. DLP4710LC DLPS178C – MAY 2020 – REVISED JULY 2023 www.ti.com 6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: DLP4710LC |
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