STM32F446VC datasheet(124/202 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F446xC/E

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DocID027107 Rev 6

Figure 33. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 59. Otherwise the reset is not taken into account by the device.

3. The external capacitor on NRST must be placed as close as possible to the device.

6.3.19

TIM timer characteristics

The parameters given in Table 60 are guaranteed by design.

Refer to Section 6.3.17: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

6.3.20

Communications interfaces

I2C interface characteristics

The I2C interface meets the requirements of the standard I2C communication protocol with

the following restrictions: the I/O pins SDA and SCL too are mapped as not “true”

open-drain. When configured as open-drain, the PMOS connected between the I/O pin and

VDD is disabled, but is still present.

Table 60. TIMx characteristics(1)(2)

Symbol

Parameter

Conditions(3)

Min

Max

Unit

tres(TIM)

Timer resolution time

AHB/APBx prescaler=1 or

2 or 4, f

TIMxCLK = 180 MHz

tTIMxCLK

AHB/APBx prescaler>4,

fTIMxCLK = 90 MHz

tTIMxCLK

fEXT

Timer external clock

frequency on CH1 to CH4

fTIMxCLK = 180 MHz

0fTIMxCLK/2

MHz

ResTIM

Timer resolution

16/32

bit

tMAX_COUNT

Maximum possible count with

32-bit counter

65536 × 65536

tTIMxCLK

1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers.

2. Guaranteed by design.

3. The maximum timer frequency on APB1 or APB2 is up to 180 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR

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