IGHL= VGVDD−VDH

RGHL+RGATE+RGFET_INT

(9)

where

• RGHL is the GH pulldown resistance

The peak GL pullup current is shown in Equation 10.

IGLH= VGVDD

RGLH+RGATE+RGFET_INT

(10)

where

• RGLH is the GL pullup resistance

The peak GL pulldown current is shown in Equation 11.

IGLL= VGVDD

RGLL+RGATE+RGFET_INT

(11)

where

• RGLL is the GL pulldown resistance

For some scenarios, if the applications require fast turnoff, an anti-paralleled diode on RGate could be used to

bypass the external gate drive resistor and speed up turnoff transition.

8.2.2.4 Estimate the Driver Power Loss

The total driver IC power dissipation can be estimated through the following components.

1. Static power losses, PQC, due to quiescent currents IGVDD and IBST is shown in Equation 12.

PQC = VGVDD × IGVDD + (VGVDD – VF) × IBST = 12V × 0.43mA + (12V – 1V) × 0.15mA = 6.8mW

(12)

2. Level-shifter losses, PIBSTS, due high-side leakage current IBSTS is shown in Equation 13.

PIBSTS = VBST × IBSTS × D = 72V × 0.033mA × 0.95 = 2.26mW

(13)

where

• D is the high-side switch duty cycle

3. Dynamic losses, PQG1&2, due to the FETs gate charge QG as shown in Equation 14.

PQG1&2=2×VGVDD×QG×fSW× RGD_R

RGD_R+RGATE+RGFET_INT= 2×12V×17nC×50kHz× 5.25Ω

5.25Ω+4.7Ω+2.2Ω

=8.8mW

(14)

where

• QG = Total FETs gate charge

• fSW = Switching frequency

• RGD_R = Average value of pullup and pulldown resistor

• RGATE = External gate drive resistor

• RGFET_INT = Internal FETs gate resistor

4. Level-shifter dynamic losses, PLS, during high-side switching due to required level-shifter charge on each

switching cycle. For this example it is assumed that value of parasitic charge QP is 2.5 nC, as shown in

Equation 15.

PLS = VBST × QP × fSW = 72V × 2.5nC × 50kHz = 9mW

(15)

LM2103

SNVSC62A – APRIL 2023 – REVISED AUGUST 2023

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