K =

POUT

POUT + PTOTAL

x 100%

-180

-156

-132

-108

-84

-60

100

1k

10k

100k

1M

FREQUENCY (Hz)

-40

-20

0

20

40

60

100

1k

10k

100k

1M

FREQUENCY (Hz)

27

LM2743

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SNVS276I – APRIL 2004 – REVISED FEBRUARY 2019

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Copyright © 2004–2019, Texas Instruments Incorporated

Typical Applications (continued)

The bandwidth and phase margin can be read graphically from Bode plots of HEA are shown in Figure 38.

Figure 37. Gain vs Frequency

Figure 38. Overall Loop Gain and Phase

The bandwidth of this example circuit is 59 kHz, with a phase margin of 60°.

8.2.1.2.9

Efficiency Calculations

The following is a sample calculation.

A reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the

Output Power (POUT) loss and the Total Power (PTOTAL) loss:

(47)

The Output Power (POUT) for the Figure 30 design is (1.2 V x 4 A) = 4.8 W. The Total Power (PTOTAL), with an

efficiency calculation to complement the design, is shown below.

The majority of the power losses are due to low and high side of MOSFET’s losses. The losses in any MOSFET

are group of switching (PSW) and conduction losses(PCND).

PFET = PSW + PCND = 61.38 mW + 270.42 mW

(48)

PFET = 331.8 mW

(49)

The following equations show FET Switching Loss (PSW).

PSW = PSW(ON) + PSW(OFF)

(50)

PSW = 0.5 x VIN x IOUT x (tr + tf) x fSW

(51)

PSW = 0.5 x 3.3 V x 4 A x 300 kHz x 31 ns

(52)

PSW = 61.38 mW

(53)

The FDS6898A has a typical turn-on rise time tr and turn-off fall time tf of 15 ns and 16 ns, respectively. The

switching losses for this type of dual N-Channel MOSFETs are 0.061 W.

The following equations show FET Conduction Loss (PCND).

PCND = PCND1 + PCND2

(54)

PCND1 = (IOUT)

2 x R

DS(ON) x k x D

(55)

PCND2 = (IOUT)

2 x R

DS(ON) x k x (1-D)

(56)

RDS(ON) = 13 mΩ and the factor is a constant value (k = 1.3) to account for the increasing RDS(ON) of a FET due to

heating.

PCND1 = (4A)

2 x 13 mΩ x 1.3 x 0.364

(57)