J

A

LM5109A

JA

T

T

P

R

T

LM5109A

12

10 A 0.95

2 10 17 n

P

C 500 kHz

7

10 V 0.6 mA

9 V 0.2 mA

7

2 V 0.5 nC

2

500 kHz

0.134 W

12

4.7

2.2

V

:

u

P u

u

u

u

u

u

u

:

:

u

u

:

GD_R

SW

GD_R

Gate

GFE

QG1

T

&

G

n

2

I t

DD

_

R

¦

R

R

R

P

2 V

Q

u

u

u

u

DD

OLL

LOL

Gate

FET_Int

V

I

R

R

R

DD

OHL

LOH

Gate

GFET_Int

V

I

R

R

R

DD

DH

OLH

HOL

Gate

GFET_Int

V

V

I

R

R

R

13

LM5109A

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SNVS412C – APRIL 2006 – REVISED SEPTEMBER 2016

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where

•

RHOL is the HO pulldown resistance

(8)

Peak LO pullup current is shown in Equation 9.

where

•

RLOH is the LO pullup resistance

(9)

Peak LO pulldown current is shown in Equation 10.

where

•

RLOL is the LO pulldown resistance

(10)

For some scenarios, if the applications require fast turnoff, an anti-paralleled diode on RGate could be used to

bypass the external gate drive resistor and speed up turnoff transition.

8.2.2.4 Estimate the Driver Power Loss

The total driver IC power dissipation can be estimated through the following components.

1. Static power losses, PQC, due to quiescent current – IDD and IHB

PQC = VDD × IDD + (VDD – VDH) × IHB

(11)

2. Level-shifter losses, PIHBS, due high-side leakage current – IHBS

PIHBS = VHB × IHBS × D

where

•

D is the high-side switch duty cycle

(12)

3. Dynamic losses, PQG1&2, due to the FETs gate charge – QG

where

•

QG = Total FETs gate charge

•

fSW = Switching frequency

•

RGD_R = Average value of pullup and pulldown resistor

•

RGate = External gate drive resistor

•

RGFET_Int = Internal FETs gate resistor

(13)

4. Level-shifter dynamic losses, PLS, during high-side switching due to required level-shifter charge on each

switching cycle – QP

PLS = VHB × QP × fSW

(14)

In this example, the estimated gate driver loss in LM5109A is shown in Equation 15.

(15)

For a given ambient temperature, the maximum allowable power loss of the IC can be defined as shown in

Equation 16.

where