LP3875-ADJ

IN

OUT

ADJ

GND

CIN

COUT

INPUT

OUTPUT

1.5 A

R1

R2

CFF

SD

SD

R1

OUT = 1.216

(1 +

)

R2

V

u

Copyright © 2016, Texas Instruments Incorporated

10 µF

10 µF

9

LP3875-ADJ

www.ti.com

SNVS247E – SEPTEMBER 2003 – REVISED AUGUST 2016

Product Folder Links: LP3875-ADJ

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Copyright © 2003–2016, Texas Instruments Incorporated

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP3875-ADJ device is an LDO linear regulator designed to provide high load current of up to 1.5 A, low

dropout voltage, and low quiescent current in shutdown mode. Figure 7 shows the typical application circuit for

this device.

8.1.1 Reverse Current Path

The internal MOSFET in the LP3875-ADJ an inherent parasitic diode. During normal operation, the input voltage

is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above

the input in an application, then current flows from the output to the input as the parasitic diode gets forward

biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200-

mA continuous and 1-A peak.

8.2 Typical Application

Figure 7. LP3875-ADJ Typical Application Circuit

8.2.1 Design Requirements

For typical linear regulator LDO applications, use the parameters listed in Table 1:

Table 1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range

2.5 V to 7 V

Output voltage

1.8 V

Output current

1.5 A

Output capacitor

10 µF

Input capacitor

10 µF

Output capacitor ESR range

100 mΩ to 4 Ω