| 전자부품 데이터시트 검색엔진 |
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LP3921 데이터시트(PDF) 42 Page - Texas Instruments |
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LP3921 데이터시트(HTML) 42 Page - Texas Instruments |
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42 / 44 page ![]() www.ti.com EXAMPLE BOARD LAYOUT 28X (0.5) (1.3) (1.3) (R0.05) TYP 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND 32X (0.6) 32X (0.24) (4.8) (4.8) (3.1) (3.1) ( 0.2) TYP VIA WQFN - 0.8 mm max height RTV0032A PLASTIC QUAD FLATPACK - NO LEAD 4224386/B 04/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM SEE SOLDER MASK DETAIL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X 1 8 9 16 17 24 25 32 33 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS |
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