8.4.2 Layout Example

Via to VPU_B

Via to GND

B

G

Legend

LSF0002DTQ

0.1µF

01005

B

GND

VBIAS

SDAA

SCLA

SCLB

4 mil

8 mil

G

SDAB

1

2

3

4

5

6

A

Via to VPU_A

01005

1 k

Via to Signal Layer

S

S

S

*Pullup Resistors are not required to be adjacent to the device, and can be present on the I

2C line elsewhere in the system

A

01005

1 k

01005

1 k

S

S

B

01005

1 k

01005

1 k

Figure 8-5. Short Trace Layout

Device PCB

TP1

SD Controller

(1.8 V IO)

TP2

LSF0108

SDIO level translator

SDIO Connnector

(3.3 V IO)

LSF010x

Figure 8-6. Device Placement

LSF0002

SDLS975 – APRIL 2024

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