ADC3681IRSBT datasheet(72/91 Pages) TI2

72 / 91 page

9.2 Initialization Set Up

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin, as shown in Figure 9-6.

1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal bandgap

reference will power up and settle out in ~ 2ms.

2. Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.

3. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses

and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock

cycles.

4. Begin programming using SPI interface.

AVDD

IOVDD

RESET

SEN

REFBUF

Ext VREF

CLK

Figure 9-6. Initialization of serial registers after power up

Table 9-5. Power-up timing

MIN

TYP

MAX

UNIT

Power-on delay: delay from power up to logic level of REFBUF pin

Delay from REFBUF pin logic level to RESET rising edge

100

RESET pulse width

Delay from RESET disable to SEN active

~ 200000

clock cycles

9.2.1 Register Initialization During Operation

If required, the serial interface registers can be cleared and reset to default settings during operation either:

• through a hardware reset or

• by applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 0x00)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

After hardware or software reset the wait time is also ~ 200000 clock cycles before the SPI registers can be

programmed.

ADC3681, ADC3682, ADC3683

SBAS872B – DECEMBER 2020 – REVISED OCTOBER 2022

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