PD

Device Fully

Powers Down

Device Fully

Powers Up

500

µs

1

µs

NOTE: The shown power−up time is based on 1

µF bypass capacitors on the reference pins.

See the Theory of Operation section for details.

SERIAL INTERFACE TIMING

Start Sequence

t

1

t

7

t

6

D7

(MSB)

D6

D5

D4

D3

D2

D1

D0

t

2

t

3

t

4

t

5

ADCLK

CS

SCLK

SDATA

Outputs change on

next rising clock edge

after CS goes high.

Data latched on

each rising edge of SCLK.

NOTE: Data is shifted in MSB first.

ADS5240

www.ti.com ...................................................................................................................................................... SBAS326E – JUNE 2004 – REVISED JANUARY 2009

LVDS TIMING DIAGRAM (PER ADC CHANNEL) (continued)

POWER-DOWN TIMING

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

t1

Serial CLK Period

50

ns

t2

Serial CLK High Time

20

ns

t3

Serial CLK Low Time

20

ns

t4

Minimum Data Setup Time

5

ns

t5

Minimum Data Hold Time

5

ns

t6

CS Fall to SCLK Rise

8

ns

t7

SCLK Rise to CS Rise

8

ns

Copyright © 2004–2009, Texas Instruments Incorporated

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