ADS5295IPFP datasheet(49/93 Pages) TI2

49 / 93 page

ADS5295

www.ti.com

SBAS595 – DECEMBER 2012

D15

D14

D13

D12

D11

D10

ENABLE 46

FALL_SDR

BIT_SER_SEL

EN_MSB_

EN_SDR

BTC_MODE

EN_2WIRE

FIRST

All bits default to '0' after reset. Note that bit D15 must be set to '1' to enable bits D[13:0].

Bit D15

ENABLE 46

This bit enables register 46h.

Bit D14

Must write '0'

Bit D13

FALL_SDR

0 = The LCLK rising or falling edge comes at the edge of the data window when operating in

SDR output mode

1 = The LCLK rising or falling edge comes in the middle of the data window when operating

in SDR output mode

Bit D12

Must write '0'

Bits D[11:8]

BIT_SER_SEL

0001 = 10-bit serialization mode enabled

0010 = 12-bit serialization mode enabled

0100 = 14-bit serialization mode enabled

1000 = 16-bit serialization mode enabled

Do not use any other bit combinations.

Bits D[7:5]

Must write '0'

Bit D4

EN_SDR

0 = DDR bit clock

1 = SDR bit clock

Bit D3

EN_MSB_FIRST

0 = LSB first

1 = MSB first

Bit D2

BTC_MODE

0 = Binary offset (ADC data output format)

1 = Twos complement (ADC data output format)

Bit D1

Must write '0'

Bit D0

EN_2WIRE

0 = One-wire LVDS output

1 = Two-wire LVDS output

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