MB85RC64TA

10

DS501-00044-5v1-E

• High Speed Mode

MB85RC64TA supports High Speed mode up to 3.4 MHz. By sending an entry command (0000 1XXX) after

start condition from the master side, it informs to the slave that the data transmission with High Speed mode

will start.

Since there is no slave side which is allowed to respond to this entry command, NACK response continues

from the slave side. After the master side recognizes this NACK response, the master side changes its state

to High Speed mode and enables the bidirectional communication up to 3.4 MHz.

By sending Stop condition, it exits out of the state in High Speed communication.

A

S

P

N

S

A2 A1

A

N P

Read

Data 8bits

1

1

010

A0

S1 X

N

X

0

000

X

AA

A

N P

Read

Data 8bits

Read

Data 8bits

Read

Data

...

...

S

A2 A1

A

A

A

A P

Address

High 8bits

Address

Low 8bits

Write

Data 8bits

0

10 1 0

A0

S1 X

N

X

0

000

X

S

A2 A1

A

A

A

A

A P

Address

High 8bits

Address

Low 8bits

Write

Data 8bits

Write

Data

0

...

10 1 0

A0

S1 X

N

X

0

000

X

S

A2 A1

A

A

A

P

Address

High 8bits

Address

Low 8bits

0

10 1 0

S

A2 A1

A

1

10 1 0

Read

Data 8bits

N

A0

A0

S1 X

N

X

0

000

X

S

A2 A1

A

A

A

Address

High 8bits

Address

Low 8bits

0

10 1 0

S

A2 A1

A

1

10 1 0

Read

Data 8bits

A

A0

A0

S1 X

N

X

0

000

X

...

A

N

Access from master

Access from slave

Start Condition

Stop Condition

ACK(SDA is the “L” level)

NACK(SDA is the “H” level)

Byte Write @High Speed Mode

Page Write @High Speed Mode

Current Address Read @High Speed Mode

Random Address Read @High Speed Mode

Sequential Read @High Speed Mode

High Speed Mode

Standard Mode

Fast Mode

Fast Mode Plus