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CDCU877BZQLR 데이터시트(PDF) 3 Page - Seme LAB

부품명 CDCU877BZQLR
상세설명  1.8-V PHASE LOCK LOOP CLOCK DRIVER
PDF  17 Pages
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제조업체  SEME-LAB [Seme LAB]
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CDCU877BZQLR 데이터시트(HTML) 3 Page - Seme LAB

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CDCU877B
1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B – JUNE 2005 – REVISED JULY 2007
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
G1
Analog ground
AVDD
H1
Analog power
CK
E1
I
Clock input with a (10 k
Ω to 100 kΩ) pulldown resistor
CK
F1
I
Complementary clock input with a (10 k
Ω to 100 kΩ) pulldown resistor
FBIN
E6
I
Feedback clock input
FBIN
F6
I
Complementary feedback clock input
FBOUT
H6
O
Feedback clock output
FBOUT
G6
O
Complementary feedback clock output
OE
F5
I
Output enable (asynchronous)
OS
D5
I
Output select (tied to GND or VDD)
B2, B3, B4, B5, C2,
GND
C5, H2, H5, J2, J3, J4,
Ground
J5
D2, D3, D4, E2, E5,
VDDQ
Logic and output power
F2, G2, G3, G4, G5
A2, A1, D1, J1, K3, A5,
Y[0:9]
O
Clock outputs
A6, D6, J6, K4
A3, B1, C1, K1, K2,
Y[0:9]
O
Complementary clock outputs
A4, B6, C6, K6, K5
FUNCTION TABLE
INPUTS
OUTPUTS
AVDD
OE
OS
CK
CK
Y
Y
FBOUT
FBOUT
PLL
GND
H
X
L
H
L
H
L
H
Bypassed/Off
GND
H
X
H
L
H
L
H
L
Bypassed/Off
GND
L
H
L
H
LZ
LZ
L
H
Bypassed/Off
LZ
LZ
GND
L
L
H
L
H
L
Bypassed/Off
Y7 Active
Y7 Active
1.8 V Nominal
L
H
L
H
LZ
LZ
L
H
On
LZ
LZ
1.8 V Nominal
L
L
H
L
H
L
On
Y7 Active
Y7 Active
1.8 V Nominal
H
X
L
H
L
H
L
H
On
1.8 V Nominal
H
X
H
L
H
L
H
L
On
1.8 V Nominal
X
X
L
L
LZ
LZ
LZ
LZ
Off
X
X
X
H
H
Reserved
3
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