STA381BWS_V01 datasheet(69/174 Pages) STMICROELECTRONICS

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STA381BWS

6.18.3

LRCK double trigger protection

This bit actively prevents double triggering of LRCLK.

6.18.4

Power-down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power stage, then the master clock to all internal hardware except the

I2C block is gated. This places the IC in a very low power consumption state.The register

state is preserved once the device recovers from power-down.

6.18.5

External amplifier power-down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This

6.19

Volume control registers (addr 0x17 - 0x1B)

6.19.1

Mute/line output configuration register (addr 0x17)

Table 50. LRCK double trigger protection

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Table 51. IC power-down

Bit

R/W

RST

Name

Description

R/W

PWDN

0: IC power-down low-power condition

1: IC normal operation

Table 52. External amplifier power-down

Bit

R/W

RST

Name

Description

R/W

EAPD

0: External power stage power-down active

1: Normal operation

LOC1

LOC0

Reserved

C3M

C2M

C1M

MMUTE

00000000

Obsolete

Product(s)

- Obsolete

Product(s)

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