STA382BWSTR datasheet(67/172 Pages) STMICROELECTRONICS

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STA382BWS

Doc ID 022784 Rev 1

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6.18.3

LRCK double trigger protection

This bit actively prevents double triggering of LRCLK.

6.18.4

Auto EAPD on clock loss

When active, this bit issues a power device power-down signal (EAPD) on clock loss

detection.

6.18.5

Power-down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power stage, then the master clock to all internal hardware except the I2C

block is gated. This places the IC in a very low power consumption state.The register state

is preserved once the device recovers from power-down.

6.18.6

External amplifier power-down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This

Table 50.

LRCK double trigger protection

Bit

R/W

RST

Name

Description

R/W

LDTE

LRCLK double trigger protection enable

Table 51.

Auto EAPD on clock loss

Bit

R/W

RST

Name

Description

R/W

ECLE

Auto EAPD on clock loss

Table 52.

IC power-down

Bit

R/W

RST

Name

Description

7R/W

PWDN

0: IC power-down low-power condition

1: IC normal operation

Table 53.

External amplifier power-down

Bit

R/W

RST

Name

Description

R/W

EAPD

0: External power stage power-down active

1: Normal operation

Obsolete

Product(s)

- Obsolete

Product(s)

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