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BQ78350-R1A

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SLUSE05 – DECEMBER 2019

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Copyright © 2019, Texas Instruments Incorporated

(1)

Specified by design. Not production tested

7.11 Electrical Characteristics: Register Backup

VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I(RB)

RB data-retention input

current

V(RB) > V(RBMIN), VCC < VIT–

1500

nA

V(RB) > V(RBMIN), VCC < VIT–, TA = 0°C

to 50°C

40

160

V(RB)

RB data-retention

voltage(1)

1.7

V

(1)

The BQ78350-R1A device times out when any clock low exceeds tTIMEOUT.

(2)

tHIGH:MAX is minimum bus idle time. SMBC = 1 for t > 50 μs causes a reset of any transaction in progress involving the BQ78350-R1A

device.

(3)

tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to stop.

(4)

tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to stop.

7.12 SMBus Timing Specifications

VCC = 2.4 V to 2.6 V, TA = –40°C to 85°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

fSMB

SMBus operating

frequency

SLAVE mode, SMBC 50% duty cycle

10

100

kHz

fMAS

SMBus master clock

frequency

MASTER mode, no clock low slave

extend

51.2

kHz

tBUF

Bus free time between

start and stop

4.7

µs

tHD:STA

Hold time after

(repeated) start

4

µs

tSU:STA

Repeated start setup

time

4.7

µs

tSU:STO

Stop setup time

4

µs

tHD:DAT

Data hold time

RECEIVE mode

0

ns

TRANSMIT mode

300

tSU:DAT

Data setup time

250

tTIMEOUT

Error signal/detect

See note(1)

25

35

ms

tLOW

Clock low period

4.7

µs

tHIGH

Clock high period

See note(2)

4

50

tLOW:SEXT

Cumulative clock low

slave extend time

See note(3)

25

ms

tLOW:MEXT

Cumulative clock low

master extend time

See note(4)

10

tF

Clock/data fall time

(VILMAX – 0.15 V) to (VIHMIN + 0.15 V)

300

ns

tR

Clock/data rise time

0.9 VCC to (VILMAX – 0.15 V)

1000