DAC7750IPWPR.B datasheet(9/56 Pages) TI2

9 / 56 page

(3)

For 0-mA to 20-mA and 0-mA to 24-mA ranges, INL is calculated beginning from code 0x0100 for DAC8750 and from code 0x0010 for

DAC7750.

(4)

Loop compliance voltage is defined as the voltage at the IOUT pin.

(5)

For stability, use slew rate limit feature or add a capacitor between IOUT and GND

7.6 Electrical Characteristics: AC

At AVDD = 10 V to 36 V, GND = 0 V, REFIN= 5 V external and DVDD = 2.7 V to 5.5 V. For IOUT, RL = 300 Ω. All

specifications –40°C to 125°C (unless otherwise noted). Typical specifications are at 25°C.

PARAMETER(1)

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DYNAMIC PERFORMANCE

Output current settling time

16-mA step, to 0.1% FSR, no L (inductance)

μs

16-mA step, to 0.1% FSR, L < 1 mH

μs

AC PSRR

200-mV, 50-Hz or 60-Hz sine wave superimposed

on power-supply voltage

–75

(1)

Specified by characterization, not production tested.

7.7 Timing Requirements: Write Mode

at TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)

MIN

MAX

UNIT

SCLK cycle time

SCLK low time

SCLK high time

LATCH delay time

LATCH high time(2)

Data setup time

Data hold time

LATCH low time

CLR pulse duration

t10

CLR activation time

µs

(1)

Specified by design, not production tested.

(2)

Based on digital interface circuitry only. When writing to DAC control and configuration registers, consider the analog output

specifications in Section 7.6.

7.8 Timing Requirements: Readback Mode

at TA = –40°C to 125°C and DVDD = 2.7 V to 5.5 V (unless otherwise noted)(1)

MIN

MAX

UNIT

t11

SCLK cycle time

t12

SCLK low time

t13

SCLK high time

t14

LATCH delay time

t15

LATCH high time

t16

Data setup time

t17

Data hold time

t18

LATCH low time

t19

Serial output delay time (CL, SDO = 15 pF)

t20

LATCH rising edge to SDO 3-state (CL, SDO = 15 pF)

(1)

Specified by design, not production tested.

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DAC7750, DAC8750

SBAS538D – DECEMBER 2013 – REVISED DECEMBER 2021

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