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DAC80504 데이터시트(PDF) 33 Page - Texas Instruments

부품명 DAC80504
상세설명  DACx0504 Quad, 16-, 14-, 12-bit, SPI voltage output DACs with internal reference
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
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DAC80504 데이터시트(HTML) 33 Page - Texas Instruments

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DAC80504, DAC70504, DAC60504
www.ti.com
SBAS871C – AUGUST 2017 – REVISED JANUARY 2019
Product Folder Links: DAC80504 DAC70504 DAC60504
Submit Documentation Feedback
Copyright © 2017–2019, Texas Instruments Incorporated
8.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]
Figure 68. CONFIG Register
15
14
13
12
11
10
9
8
Reserved
ALM-SEL
ALM-EN
CRC-EN
FSDO
DSDO
REF-PWDWN
—
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Reserved
DAC3-PWDWN DAC2-PWDWN DAC1-PWDWN DAC0-PWDWN
—
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
Reserved
—
00
Reserved for factory use
13
ALM-SEL
R/W
0
ALARM select.
0: ALARM pin is CRC-ERROR
1: ALARM pin is REF-ALARM
12
ALM-EN
R/W
0
Configure SDO/ALARM pin. When 1: SDO/ALARM pin is an
active-low, open-drain, alarm pin. An external 10 kΩ pullup
resistor to VIO is required. FSDO and DSDO bits are ignored.
When 0: SDO/ALARM pin is a serial interface, push-pull, SDO
pin
11
CRC-EN
R/W
0
CRC enable bit. Set to 1 to enable CRC. Set to 0 to disable
10
FSDO
R/W
0
Fast SDO bit (half-cycle speedup). When 0, SDO updates on an
SCLK rising edge. When 1, SDO updates a half-cycle earlier,
during an SCLK falling edge.
9
DSDO
R/W
0
Disable SDO bit. When 1, SDO is always tri-stated. When 0,
SDO is driven while CS is low, and tri-stated while CS is high
8
REF-PWDWN
R/W
0
When set to 1 disables the device internal reference
7:4
Reserved
—
0000
Reserved for factory use
3
DAC3-PWDWN
R/W
0
When set to 1 the corresponding DAC is set in power-down
mode and its output is connected to GND through a 1 k
Ω
internal resistor.
2
DAC2-PWDWN
R/W
0
1
DAC1-PWDWN
R/W
0
0
DAC0-PWDWN
R/W
0



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