Serial peripheral interface (SPI)

L9733

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DocID11319 Rev 12

5.4

Serial clock (SCLK)

This is the clock signal input for synchronization of serial data transfer. DI data is shifted into

the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.

The SCLK input has a nominal 100 kΩ resistor connected from this pin to the VDO pin,

which pulls this pin to VDO if an open circuit condition occurs.

5.5

Initial input command register and fault register SPI cycle

After initial application of Vdd to the L9733, the input command register and the fault register

are "Cleared" by the POR circuitry and that means that the default condition for the output

status is Off, the default diagnostic mode is No Latch and the switching OFF overcurrent

protection is enable. During the initial SPI cycle, and all subsequent cycles, valid fault data

will be clocked out of DO (fault bits).

5.6

Input command register

An input byte (16 bits) is routed to the Command Register. The content of this Command

Register is given in Table 10. Additional DI data will continue to be wrapped around the DO

pin. If CS should happen to go high before complete reception of the current byte, this just

transmitted byte shall be ignored (invalid).

Table 9. Bit command register definition

Key word

Writing mode: output

Output status

MSB

LSB

1

0

1

0

1100

OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Key word

Writing mode: diag

Driver diag mode

MSB

LSB

1

0

1

0

0011

Diag 8 Diag 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Key word

Writing mode: protect

Driver overcurrent protection

MSB

LSB

1

0

1

0

1010

Ilim 8 Ilim 7 Ilim 6 Ilim 5 Ilim 4 Ilim 3 Ilim 2 Ilim 1

b15

b14

b13

b12

b11

b10

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0