Functional description

L9848

18/27

3.7.1

Initial fault register SPI Cycle

After initial application of VDD to the L9848, the fault register is "Cleared" by the POR

circuitry during the initial SPI cycle, and all subsequent cycles, valid fault data will be clocked

out of DO (fault bits). The bits that are "Set" indicate which particular output(s) have a fault

condition.

3.7.2

Incandescent lamp outputs

Software filtering may be needed to ignore fault signals due to the long turn on delay

associated with lamp loads. For example, the lamp load channel gets enabled during one

SPI cycle. Approximately 20ms-100ms later, a SPI cycle is required to read the correct fault

latch data, which will be cleared after the falling edge of CS of that SPI cycle.

3.8

Configuration for Output1-6

The drain and source pins for each output must be connected in one of the two following

configurations (see Figure 6a and Figure 6b).

3.8.1

Low side drivers

When any combination of Output1-6 are connected in a low side drive configuration the

source of the applicable output (SRC1-6) has to be connected to ground. The drain of the

applicable output (DRN1-6) has to be connected to the low side of the load.

3.8.2

High side drivers

When any combination of Output1-6 are connected in a high side drive configuration the

drain of the applicable output (DRN1-6) has to be connected to VBatt. The source of the

applicable output (SRC1-6) has to be connected to the high side of the load.

3.9

DRN1-6 susceptibility to negative voltage transients

For any output(s) connected and used for a high side drive a fast negative transient slew

rate does not inadvertently issue a POR (power on reset) or cause parasitic latching to

occur. Nevertheless under some conditions it may be necessary to have a ceramic chip

capacitor of 10nF to 100nF connected from drain to GND to aid in preventing the occurance

of a problem due to very fast negative transient(s) on the drain(s) of the device.