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DRV8874PWPRG4 데이터시트(PDF) 19 Page - Texas Instruments |
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DRV8874PWPRG4 데이터시트(HTML) 19 Page - Texas Instruments |
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19 / 42 page ![]() 19 DRV8874 www.ti.com SLVSF66A – AUGUST 2019 – REVISED DECEMBER 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Device Functional Modes (continued) 7.4.2 Low-Power Sleep Mode The DRV887x family of devices support a low power mode to reduce current consumption from the VM pin when the driver is not active. This mode is entered by setting the nSLEEP pin logic low and waiting for tSLEEP to elapse. In sleep mode, the H-bridge, charge pump, internal 5-V regulator, and internal logic are disabled. The device relies on a weak pulldown to ensure all of the internal MOSFETs remain disabled. The device will not respond to any inputs besides nSLEEP while in low-power sleep mode. 7.4.3 Fault Mode The DRV887x family of devices enter a fault mode when a fault is encountered. This is utilized to protect the device and the output load. The device behavior in the fault mode is described in Table 7 and depends on the fault condition. The device will leave the fault mode and re-enter the active mode when the recovery condition is met. |
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