GND

PA_IN

LNA_OUT

GND

GND

PA_OUT

GND

TR_SW

1

2

3

4

12

11

10

9

5

6

7

8

16

15

14

13

4x4QFN-16

CC1190

SWRS089 A – NOVEMBER 2009 – REVISED FEBRUARY 2010

www.ti.com

DEVICE INFORMATION

QFN-16 PACKAGE

TOP VIEW

NOTE

The exposed die attach pad must be connected to a solid ground plane as this is the

primary ground connection for the chip. Inductance in vias to the pad should be

minimized. Following the CC1190EM reference layout is recommended. Changes will alter

the performance. Also see the PCB land pattern information in this data sheet.

PIN FUNCTIONS

PIN

I/O

DESCRIPTION

NO.

NAME

The exposed die attach pad must be connected to a solid ground plane. See CC1190EM

-

GND

Ground

(SWRR064) reference design for recommended layout.

1

GND

Ground

Secondary ground connection. Should be shorted to the die attach pad on the top PCB layer.

2

PA_OUT

RF

Output of PA.

3

GND

Ground

Secondary ground connection. Should be shorted to the die attach pad on the top PCB layer.

4

TR_SW

RF

RXTX switch pin.

5

LAN_IN

RF

Input of LNA.

Digital control pin.

6

HGM

Digital Input

HGM = 1

→ Device in High Gain Mode.

HGM = 0

→ Device in Low Gain Mode.

7

LNA_EN

Digital Input

Digital control pin. See Table 2 and Table 3 for details.

8

PA_EN

Digital Input

Digital control pin. See Table 2 and Table 3 for details.

9

GND

Ground

Secondary ground connection. Should be shorted to the die attach pad on the top PCB layer.

10

LNA_OUT

RF

Output of LNA.

11

PA_IN

RF

Input of PA.

12

GND

Ground

Secondary ground connection. Should be shorted to the die attach pad on the top PCB layer.

13

VDD_LNA

Power

2 – 3.7 V Supply Voltage.

14

BIAS

Analog

Biasing input. Resistor between this node and ground sets bias current.

15

VDD_PA2

Power

2 – 3.7 V Supply Voltage.

16

VDD_PA1

Power

2 – 3.7 V Supply Voltage.

4

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