CD74ACT157 Quadruple 2-Line to 1-Line Data Selector/Multiplexer

1 Features

• Inputs are TTL-voltage compatible

• Speed of bipolar F, AS, and S, with significantly

reduced power consumption

• Balanced propagation delays

• ±24mA output drive current

– Fanout to 15F devices

• SCR-latchup-resistant CMOS process and circuit

design

• Exceeds 2kV ESD protection per MIL-STD-883,

method 3015

2 Applications

• Data selection

• Multiplexing

3 Description

This quadruple 2-line to 1-line data selector/

multiplexer is designed for 4.5V to 5.5V VCC

operation.

Package Information

PART NUMBER

PACKAGE(1)

PACKAGE SIZE(2)

BODY SIZE(3)

CD74ACT157

D (SOIC, 16)

9.90mm × 6mm

9.90mm × 3.90mm

N (PDIP, 16)

19.31mm × 9.4mm

19.31mm × 6.35mm

PW (TSSOP, 16)

5.00mm × 6.4mm

5.00mm × 4.40mm

BQB (WQFN, 16)

3.5mm × 2.5mm

3.5mm × 2.5mm

(1)

For more information, see Section 11.

(2)

The package size (length × width) is a nominal value and

includes pins, where applicable.

(3)

The body size (length × width) is a nominal value and does

not include pins.

A/B

xA

xB

xY

G

Logic Diagram (Positive Logic)

CD74ACT157

SCHS340D – MARCH 2003 – REVISED JULY 2025

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.