INP

INN

DIV

/1 /2 /4

QP0

QN0

QP1

QN1

QDP

QDN

QP2

QN2

70 W

V

T

70 W

200 kW

VCC

GND

200 kW

Copyright © 2016, Texas Instruments Incorporated

9

CDCLVD1213

www.ti.com

SCAS897A – JULY 2010 – REVISED OCTOBER 2016

Product Folder Links: CDCLVD1213

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Copyright © 2010–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The CDCLVD1213 LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing

and termination are required to ensure correct operation of the device and to maximize signal integrity.

The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the

receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI

recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage

different than the output common-mode voltage of the CDCLVD1213, AC-coupling must be used. If the LVDS

receiver has internal 100-Ω termination, external termination must be omitted.

8.2 Functional Block Diagram

8.3 Feature Description

The CDCLVD1213 is a low additive jitter LVDS fan-out buffer that can generate four copies of an LVPECL,

LVDS, or CML input, one of which can be frequency divided by a factor of 1, 2, or 4. The CDCLVD1213 can

accept reference clock frequencies up to 800 MHz while providing low output skew.

8.4 Device Functional Modes

The divider on output QD can be configured to divide the input frequency by a factor 1, 2, or 4 through the

control pin (see Table 1). Unused outputs can be left floating to reduce overall component cost. Both AC- and

DC-coupling schemes can be used with the CDCLVD1213 to provide greater system flexibility.

Table 1. Divider Selection Table

DIV

DIVIDER RATIO

0

/1

open

/2

1

/4