CDCLVD2106

Z = 50 W

Z = 50 W

LVDS

100 W

V

AC_REF

100 nF

50 W

Z = 50 W

Z = 50 W

CDCLVD2106

50 W

LVDS

100 nF

150 W

150 W

V

AC_REF

100 nF

50 W

Z = 50 W

Z = 50 W

CDCLVD2106

50 W

LVPECL

75 W

75 W

100 nF

CDCLVD2106

www.ti.com

SCAS902B – SEPTEMBER 2010 – REVISED JANUARY 2011

INPUT TERMINATION

The CDCLVD2106 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers.

LVDS Driver can be connected to CDCLVD2106 inputs with dc or ac coupling as shown Figure 15 and Figure 16

respectively.

Figure 17 shows how to connect LVPECL inputs to the CDCLVD2106. The series resistors are required to

reduce the LVPECL signal swing if the signal swing is >1.6 VPP.

Figure 18 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2106 directly. The series

resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs

to be limited to VIH ≤ VCC.

Figure 15. LVDS Clock Driver Connected to CDCLVD2106 Input (DC coupled)

spacer

Figure 16. LVDS Clock Driver Connected to CDCLVD2106 Input (AC coupled)

spacer

Figure 17. LVPECL Clock Driver Connected to CDCLVD2106 Input

Copyright © 2010–2011, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Link(s): CDCLVD2106