CY74FCT652T

8-BIT REGISTERED TRANSCEIVER

WITH 3-STATE OUTPUTS

SCCS032B – SEPTEMBER 1994 – REVISED OCTOBER 2001

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ORDERING INFORMATION

TA

PACKAGE†

SPEED

(ns)

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QSOP – Q

Tape and reel

5.4

CY74FCT652CTQCT

FCT652C

SOIC

SO

Tube

5.4

CY74FCT652CTSOC

FCT652C

SOIC – SO

Tape and reel

5.4

CY74FCT652CTSOCT

FCT652C

–40

°C to 85°C

QSOP – Q

Tape and reel

6.3

CY74FCT652ATQCT

FCT652A

SOIC

SO

Tube

6.3

CY74FCT652ATSOC

FCT652A

SOIC – SO

Tape and reel

6.3

CY74FCT652ATSOCT

FCT652A

QSOP – Q

Tape and reel

9

CY74FCT652TQCT

FCT652

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

INPUTS

DATA I/O

OPERATION OR

GAB

GBA

CPAB

CPBA

SAB

SBA

A1–A8

B1–B8

FUNCTION

L

H

H or L

H or L

X

X

Input

Input

Isolation

L

H

↑

↑

X

X

Input

Input

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified§

Store A, hold B

H

H

↑

↑

X‡

X

Input

Output

Store A in both registers

L

X

H or L

↑

X

X

Unspecified§

Input

Hold A, store B

L

L

↑

↑

XX‡

Output

Input

Store B in both registers

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

H or L

X

H

Output

Input

Stored B data to A bus

H

H

X

X

L

X

Input

Output

Real-time A data to B bus

H

H

H or L

X

H

X

Input

Output

Stored A data to B bus

H

L

H or L

H or L

H

H

Output

Output

Stored A data to B bus and

Stored B data to A bus

H = High logic level, L = Low logic level, X = Don’t care,

↑ = Low-to-high transition

‡ Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both

registers.

§ The data output functions can be enabled or disabled by various signals at the GAB and GBA inputs. Data input functions

always are enabled, i.e., data at the bus pins are stored on every low-to-high transition of the clock inputs.