L9907TR datasheet(29/49 Pages) STMICROELECTRONICS

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DS11800 Rev 5

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L9907

SPI operation

The L9907 SPI is a standard 16-bit, four wire interface. By means of the SPI most device

parameters can be internally set and the fault diagnostic can be read.

The timing diagram for the SPI operation is reported in Figure 7 below. The IC reads the

input data at SDI pin on the falling edge of the SPI clock (SCK). The IC outputs the SPI data

at SDO pin on the rising edge of the SPI clock (SCK).

Figure 7. Timing diagram for the SPI operation.

The SPI protocol integrates an internal check to add robustness to the communication: a

writing attempt of a not allowed register, an incorrect parity frame or a wrong number of bits

(different than 16) results in a "SPI error bit", that is available at SDO immediately after

asserting CS the next time and before starting the SCK toggling.

If the current SPI cycle is affected by a communication error, the current SDI command is

rejected and a SPI error message (0xB001) is presented as SDO response at the following

SPI cycle.

SCK

SDO

SPI error

Bi t ( 15) MS B

Bi t(14:1)

Bit(0)

LSB

SDI

MSB IN

Bi t(14:1)

LSB I N

SCK

SDO

SPI error

Bi t ( 15) MS B

Bi t(14:1)

Bit(0)

LSB

SDI

MSB IN

Bi t(14:1)

LSB I N

GAPGPS00838

Table 22. SPI timing specifications

Parameter

Condition

Min.

Typ.

Max.

Unit

SCK Frequency (fSCK)1

MHz

SCK High/low time (tSCK-high, t-SCK-low)

1a, 1b

Enable lead time (tlead)2

740

Enable lag time (tlag)3

200

Data valid time (tvalid)

Cload<60pF

@ fSCK=8MHz

Data set up time (tSI-set)

Data hold time (tSI-hold)

Disable time (tdisable)

120

SCK, SI rise/fall time (trise, tfall)-

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