| 전자부품 데이터시트 검색엔진 |
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ISO6760F 데이터시트(PDF) 26 Page - Texas Instruments |
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ISO6760F 데이터시트(HTML) 26 Page - Texas Instruments |
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26 / 50 page ![]() 7 Parameter Measurement Information IN OUT CL See Note B VO VI VOL VOH VCCI 0 V tr 50 Input Generator (See Note A) VI VO tf tPLH tPHL 50% 50% 50% 50% 90% 10% Copyright © 2016, Texas Instruments Incorporated A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 7-1. Switching Characteristics Test Circuit and Voltage Waveforms VI VCC IN OUT VO CL See Note A IN = 0 V (Devices without suffix F) IN = VCC (Devices with suffix F) VO VI VOL VOH VCC 0 V 1.4 V 50% tDO default high default low See Note B A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. Power Supply Ramp Rate = 10 mV/ns Figure 7-2. Default Output Delay Time Test Circuit and Voltage Waveforms IN OUT VCCO GNDI + ± VCM + ± VOH or VOL VCCI Pass-fail criteria: The output must remain stable. CL See Note A S1 GNDO A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. For optimized CMTI performance, a 0.1 μF + 1 μF decoupling capacitor should be placed close to VCC1 and VCC2. Please see Section 11.2 for capacitor placement details. A recommended 0.1μF capacitor is LLL185R71A104MA11L (CAP CER 0.1UF 10V X7R 0306 - LW Reversed Low ESL Chip Ceramic Capacitors) or equivalent. Figure 7-3. Common-Mode Transient Immunity Test Circuit ISO6760, ISO6761, ISO6762, ISO6763 SLLSFK0E – AUGUST 2021 – REVISED FEBRUARY 2023 www.ti.com 26 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ISO6760 ISO6761 ISO6762 ISO6763 |
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