ISO7730DWR.B datasheet(32/50 Pages) TI2

32 / 50 page

DUT

Vcc 2

Vcc 1

GND 1

GND 2

Oven at 150°C

Time Counter

> 1mA

Figure 8-7. Test Setup for Insulation Lifetime Measurement

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

200

1200

2200

3200

4200

5200

6200

50 %

Applied Voltage (VRMS)

54 years

36 years

20%

VDE safety margin zone

Operating zone

TDDB (<1ppm fail rate)

Figure 8-8. Insulation Lifetime Projection Data

8.3 Power Supply Recommendations

To help provide reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended

at the input and output supply pins (VCC1 and VCC2). The capacitors must be placed as close to the supply

pins as possible. If only a single primary-side power supply is available in an application, isolated power can be

generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501 or

SN6505A. For such applications, detailed power supply design and transformer selection recommendations are

available in the SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505A Low-Noise 1-A

Transformer Drivers for Isolated Power Supplies (SLLSEP9).

8.4 Layout

8.4.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 8-9). Layer stacking must

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

ISO7730, ISO7731

SLLSES0K – SEPTEMBER 2016 – REVISED SEPTEMBER 2025

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