TDA7801PDTR datasheet(32/48 Pages) STMICROELECTRONICS

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I2S bus interface

TDA7801

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DocID022674 Rev 4

7.1

Interface timings requirements

The data interface timings are described below. In the TDA7801 the TDM format as shown

in Figure 34, is an I2S extended: if the four channels option is set then the serial clock is

multiplied by two while it will be multiplied by four when the eight channels option is set. This

means that it is important to keep a duty-cycle of 50% for the Word Select signal and

moreover, all the timings for serial clock and data don't change in every I2S configuration.

Table 9 shows the values of system clock frequencies (serial clock SCK) for common audio

sampling frequencies.

Figure 12 shows the detail of the audio input format as specified by the standard I2S

specification. When more channels are sent the input format does not change and they

follow the sequence as shown in Figure 34.

Figure 36. Audio data input format

Figure 37. Audio interface timing

Table 9. System clock frequencies for common audio sampling frequencies

Frequency

sampling (fs)

System clock frequency (fSCK), (MHz)

I2S standard

(fs*64)

TDM 4ch (fs*128)

TDM 8ch md1

(fs*256)

TDM 8ch md2

(fs*256)

44.1 (kHz)

2.82

5.64

11.29

48.0 (kHz)

3.07

6.14

12.29

96.0 (kHz)

6.14

12.29

24.58

192.0 (kHz)

12.29

24.58

N.A.

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