PAC1932SLASH3SLASH4 datasheet(26/62 Pages) MICROCHIP

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PAC1932/3/4

DS20005850C-page 26

 2017-2018 Microchip Technology Inc.

5.0

SMBUS AND I2C

COMMUNICATIONS

PROTOCOL

The PAC1932/3/4 communicates over a two-wire bus

with a controller using SMBus or I2C serial

communication protocol. A detailed timing diagram is

shown in Figure 1-1.

Stretching of the SMCLK signal is supported; however,

the PAC1932/3/4 will not stretch the clock signal.

5.1

I2C/SMBus Addressing and

Control Bits

5.1.1

SMBUS ADDRESS AND RD/WR BIT

The SMBus Address Byte consists of the 7-bit slave

address followed by a 1-bit RD / WR indicator. If this

RD / WR bit is a logic ‘0’, the SMBus master is writing

data to the slave device. If this RD / WR bit is a logic

‘1’, the SMBus master is reading data from the slave

device.

The PAC1932/3/4 I2C/SMBus address is determined

by a single pull-down resistor connected between

ground and the ADDRSEL pin as shown in Table 5-1.

The chip translates the resistor value into an address

on power-up, and the value is latched until another

power-up event takes place. The address cannot be

changed on the fly.

5.1.2

SMBUS START BIT

The SMBus Start bit is defined as a transition of the

SMBus data line from a logic ‘1’ state to a logic ‘0’ state

while the SMBus Clock line is in a logic ‘1’ state.

5.1.3

SMBUS ACK AND NACK BITS

The SMBus slave will ACK (acknowledge) all data

bytes that it receives. This is done by the slave device

pulling the SMBus data line low after the eighth bit of

each byte that is transmitted.

5.1.4

SMBUS STOP BIT

The SMBus Stop bit is defined as a transition of the

SMBus data line from a logic ‘0’ state to a logic ‘1’ state

while the SMBus clock line is in a logic ‘1’ state. When

the PAC1932/3/4 detects an SMBus Stop bit, and it has

been communicating with the SMBus protocol, it will

reset its slave interface and prepare to receive further

communications.

5.1.5

SMBUS DATA BYTES

All SMBus data bytes are sent most significant bit first

and composed of eight bits of information.

TABLE 5-1:

ADDRESS SELECT

RESISTOR

Resistor (1%)

SMBus Address

0 (Tie to GND)

0010_000(r/w)

499

0010_001(r/w)

806

0010_010(r/w)

1,270

0010_011(r/w)

2,050

0010_100(r/w)

3,240

0010_101(r/w)

5,230

0010_110(r/w)

8,450

0010_111(r/w)

13,300

0011_000(r/w)

21,500

0011_001(r/w)

34,000

0011_010(r/w)

54,900

0011_011(r/w)

88,700

0011_100(r/w)

140,000

0011_101(r/w)

226,000

0011_110(r/w)

Tie to VDD

0011_111(r/w)

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