10.2.1.1 Design Requirements

PARAMETERS

VALUES

Supply Voltage Range

3.5 V to 8.5 V

Input Voltage Range

20 mVRMS to VCC + 0.5

Input Frequency

1 Hz to 500 kHz

Output Current

Max. 15 mA

10.2.1.2 Detailed Design Procedure

10.2.1.2.1 Timing Components

To calculate the timing components for an approximated desired central detection frequency (f0), the timing

capacitor value (C1) should be stated in order to calculate the timing resistor value (R1). Typically for most

applications, a 0.1-µF capacitor is used.

fo = 1 / (1.1 × R1 × C1)

(2)

10.2.1.2.2 Bandwidth

Detection bandwidth is represented as a percentage of f0. It can be selected based on the input voltage levels

(Vi). For Vi < 200 mVRMS,

(3)

For Vi > 200 mVRMS, refer to Table 9-2 or Figure 7-5.

10.2.1.2.3 Output Filter

The output filter selection is made considering the capacitor value to be at least twice the Loop filter capacitor.

C3 ≥ 2C2

(4)

10.2.1.3 Application Curve

IN (PIN 3)

OUT (PIN 8)

Figure 10-2. Frequency Detection

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LM567, LM567C

SNOSBQ4F – MAY 1999 – REVISED JANUARY 2022

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