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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA1085 데이터시트(PDF) 41 Page - STMicroelectronics |
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STA1085 데이터시트(HTML) 41 Page - STMicroelectronics |
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41 / 127 page  DS13319 Rev 2 41/127 STA108x, STA109x Signal description 126 JTAG1_TMS GPIO107(1) S_GPIO2 T11 C5 I VDD_IO JTAG1. Test Mode Select. This is an optional JTAG interface, not enabled by default. If enabled, it connects to Cortex-R4 only and allows the parallel debugging of the Cortex-R4 and Cortex-M3 processors without chaining them but using two separate JTAG interfaces. If JTAG1 is not enabled, the debug interface is controlled through the JTAG dedicated interface only. JTAG1_TRSTn GPIO108(1) S_GPIO3 R11 A5 I VDD_IO JTAG1. Test Reset not. This is an optional JTAG interface, not enabled by default. If enabled, it connects to Cortex-R4 only and allows the parallel debugging of the Cortex-R4 and Cortex-M3 processors without chaining them but using two separate JTAG interfaces. If JTAG1 is not enabled, the debug interface is controlled through the JTAG dedicated interface only. 1. Only available on STA109x. Table 15. Debug signals (continued) Name GPIOs Balls DIR Power Domain Description |
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