ESDA25DB3RL datasheet(3/5 Pages) STMICROELECTRONICS

3 / 5 page

The ESDA family has been designed to clamp fast

spikes like ESD. Generally the PCB designers

need to calculate easily the clamping voltage VCL.

This is why we give the dynamic resistance in

addition to the classical parameters. The voltage

across the protection cell can be calculated with

the following formula:

VCL =VBR +Rd IPP

WhereIpp is the peakcurrent throughthe ESDAcell.

DYNAMIC RESISTANCE MEASUREMENT

The short duration of the ESD has led us to prefer

a more adapted test wave, as below defined, to the

classical 8/20

µs and 10/1000µs surges.

2.5

µs durationmeasurement wave.

As the value of the dynamic resistance remains

stable for a surge duration lower than 20

µs, the

2.5

µs rectangularsurge is well adapted. In addition

both rise and fall times are optimized to avoid any

parasitic phenomenon during the measurement of

Rd.

CALCULATION OF THE CLAMPING VOLTAGE

USE OF THE DYNAMIC RESISTANCE

µs

tp = 2.5

µs

Ipp

ESDA25DB3

3/5

ESDA25DB3RL 데이터시트(PDF) 3 Page - STMicroelectronics