M41TC8025 datasheet(20/41 Pages) STMICROELECTRONICS

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Operation

M41TC8025

20/41

DocID022873 Rev 4

2.6.2

Fixed-cycle timer interrupt interval configuration

Table 16 gives examples of the possible periods for the fixed-cycle timer interrupt.

2.6.3

Time error in fixed-cycle timer interrupt

Before configuring the fixed-cycle timer interrupt conditions, for example, setting the values

in register 0Bh and 0Ch or selecting the source clock, it is recommended to write "0" to both

the TE and TIE bits to prevent hardware interrupts during the configuration period.

When the TE bit is set from 0 to 1, the first interrupt may not be generated correctly. The

maximum time error could be as much as the source clock period as illustrated below in

Figure 10.

In a similar way, if the user sets the RESET bit to 1, the fraction of the internal clock chain

below 4 kHz will be cleared. This can also result in an error in the first interrupt once the

RESET bit is cleared. This timing error does not affect the 4 kHz clock source fixed-cycle

interrupt.

Figure 10. Fixed-cycle interrupt - first interrupt time error

Table 16. Fixed-cycle timer interrupt configuration

Timer counter

setting

Source clock

4096 Hz

TSEL1,0 = 0,0

64 Hz

TSEL1,0 = 0,1

“Second” update

1 Hz

TSEL1,0 = 1,0

“Minute” update

TSEL1,0 = 1,1

244.14 μs

15.625 ms

1 s

1 min

488.28 μs

31.25 ms

2 s

2 min

...

10.01 ms

640.63 ms

41 s

41 min

205

50.049 ms

3.203 s

205 s

205 min

410

100.1 ms

6.406 s

410 s

410 min

2048

500 ms

32 s

2048 s

2048 min

...

4095

0.9998 s

63.984 s

4095 s

4095 min

Obsolete

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