S24CS02A datasheet(19/47 Pages) SII

19 / 47 page

2-WIRE CMOS SERIAL E2PROM

Rev.4.4_00

S-24CS01A/02A/04A/08A

Seiko Instruments Inc.

8. Address Increment Timing

The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the

read data in read operation and the falling edge of the SCL clock for the 8th bit of the received data in write

operation.

SCL

SDA

R / W=1

Address Increment

891

D7 Output

D0 Output

ACK Output

Figure 19 Address Increment Timing in Reading

SCL

SDA

R / W=0

891

D7 Input

D0 Input

ACK Output

Address Increment

Figure 20 Address Increment Timing in Writing

Write Inhibition Function at Low Power Voltage

The S-24CS01A/02A/04A/08A have a detection circuit for low power voltage. The detection circuit cancels

a write instruction when the power voltage is low or the power switch is on. The detection voltage is 1.75 V

typically and the release voltage is 2.05 V typically, the hysteresis of approximate 0.3 V thus exists. (See

Figure 21

When a low power voltage is detected, a write instruction is canceled at the reception of a stop condition.

When the power voltage lowers during a data transmission or a write operation, the data at the address of

the operation is not assured.

Power supply voltage

Write Instruction

cancel

Release voltage (+VDET)

2.05 V typ.

Detection voltage (-VDET)

1.75 V typ.

Hysteresis width

0.3 V approximately

Figure 21 Operation at low power voltage

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