LP5907 datasheet(17/50 Pages) TI2

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7.4 Layout

7.4.1 Layout Guidelines

The dynamic performance of the LP5907 is dependent on the layout of the PCB. PCB layout practices that are

adequate for typical LDOs can degrade the PSRR, noise, or transient performance of the LP5907.

Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907, and as

close to the package as practical. The ground connections for CIN and COUT must route back to the LP5907

ground pin using as wide and short of a copper trace as practical.

Connections using long trace lengths, narrow trace widths, and connections through vias must be avoided.

These connections add parasitic inductances and resistance that results in inferior performance, especially

during transient conditions.

7.4.1.1 X2SON Mounting

The X2SON package thermal pad must be soldered to the printed circuit board for proper thermal and

mechanical performance. For more information, see the QFN/SON PCB Attachment application note.

7.4.1.2 DSBGA Mounting

The DSBGA package requires specific mounting techniques, which are detailed in AN-1112 DSBGA Wafer Level

Chip Scale Package application note. For best results during assembly, alignment ordinals on the PC board can

be used to facilitate placement of the DSBGA device.

7.4.1.3 DSBGA Light Sensitivity

Exposing the DSBGA device to direct light can cause incorrect operation of the device. Light sources such

as halogen lamps can affect electrical performance if these sources are situated in proximity to the device.

Light with wavelengths in the red and infrared part of the spectrum have the most detrimental effect; thus, the

fluorescent lighting used inside most buildings has very little effect on performance.

7.4.2 Layout Examples

GND

OUT

N/C

CIN

COUT

VIN

GND

Enable

VOUT

GND

Figure 7-4. SOT-23 Typical Layout

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LP5907

SNVS798Q – APRIL 2012 – REVISED JULY 2025

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LP5907 데이터시트(PDF) 17 Page - Texas Instruments