 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
LP5569RTWRG4 데이터시트(PDF) 8 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
LP5569RTWRG4 데이터시트(HTML) 8 Page - Texas Instruments |
|
|
8 / 93 page  8 LP5569 SNVSAP8A – JULY 2017 – REVISED SEPTEMBER 2017 www.ti.com Product Folder Links: LP5569 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.10 Serial-Bus Timing Requirements (SDA, SCL), See Figure 1 I 2C fast mode MIN MAX UNIT ƒSCL Clock frequency 0 400 kHz 1 Hold time (repeated) START condition 0.6 µs 2 Clock low time 1.3 µs 3 Clock high time 600 ns 4 Setup time for a repeated START condition 600 ns 5 Data hold time 0 ns 6 Data setup time 100 ns 7 Rise time of SDA and SCL 20 + 0.1Cb 300 ns 8 Fall time of SDA and SCL 15 + 0.1Cb 300 ns 9 Setup time for STOP condition 600 ns 10 Bus-free time between a STOP and a START condition 1.3 µs Cb Capacitive load for each bus line 10 200 pF 7.11 External Clock Timing Requirements (CLK), See Figure 2 over operating ambient temperature range (unless otherwise noted) MIN TYP MAX UNIT ƒCLK Clock frequency 32.7 kHz tCLKH High time 6 µs tCLKL Low time 6 µs tr Clock rise time, 10% rising edge to 90% rising edge 2 µs tf Clock fall time, 90% falling edge to 10% falling edge 2 µs Figure 1. Timing Parameters Figure 2. External Clock Signal |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
