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MSP430F14X 데이터시트(PDF) 42 Page - Texas Instruments |
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MSP430F14X 데이터시트(HTML) 42 Page - Texas Instruments |
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42 / 88 page ![]() 42 MSP430F149, MSP430F148, MSP430F147 MSP430F1491, MSP430F1481, MSP430F1471 MSP430F135, MSP430F133 SLAS272H – JULY 2000 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471 MSP430F135 MSP430F133 Detailed Description Copyright © 2000–2018, Texas Instruments Incorporated (1) Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2). Table 6-13. Timer_B3 and Timer_B7 Signal Connections(1) INPUT PIN NUMBER DEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK MODULE OUTPUT SIGNAL OUTPUT PIN NUMBER 43 - P4.7 TBCLK TBCLK Timer NA ACLK ACLK SMCLK SMCLK 43 - P4.7 TBCLK INCLK 36 - P4.0 TB0 CCI0A CCR0 TB0 36 - P4.0 36 - P4.0 TB0 CCI0B ADC12 (internal) DVSS GND DVCC VCC 37 - P4.1 TB1 CCI1A CCR1 TB1 37 - P4.1 37 - P4.1 TB1 CCI1B ADC12 (internal) DVSS GND DVCC VCC 38 - P4.2 TB2 CCI2A CCR2 TB2 38 - P4.2 38 - P4.2 TB2 CCI2B DVSS GND DVCC VCC 39 - P4.3 TB3 CCI3A CCR3 TB3 39 - P4.3 39 - P4.3 TB3 CCI3B DVSS GND DVCC VCC 40 - P4.4 TB4 CCI4A CCR4 TB4 40 - P4.4 40 - P4.4 TB4 CCI4B DVSS GND DVCC VCC 41 - P4.5 TB5 CCI5A CCR5 TB5 41 - P4.5 41 - P4.5 TB5 CCI5B DVSS GND DVCC VCC 42 - P4.6 TB6 CCI6A CCR6 TB6 42 - P4.6 ACLK (internal) CCI6B DVSS GND DVCC VCC |
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