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M41T81

Clock operation

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Figure 13. Backup mode alarm waveform

3.5

Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the watchdog

register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits

RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second,

and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of

the five-bit multiplier value with the resolution. (For example: writing 00001110 in the

watchdog register = 3*1, or 3 seconds). If the processor does not reset the timer within the

specified period, the M41T81 sets the WDF (watchdog flag) and generates a watchdog

interrupt.

The watchdog timer can be reset by having the microprocessor perform a WRITE of the

watchdog register. The time-out period then starts over.

Should the watchdog timer time-out, a value of 00h needs to be written to the watchdog

register in order to clear the IRQ/FT/OUT/SQW pin. This will also disable the watchdog

function until it is again programmed correctly. A READ of the flags register will reset the

watchdog flag (bit D7; register 0Fh).

The watchdog function is automatically disabled upon power-up and the watchdog register

is cleared. If the watchdog function is set, the frequency test function is activated, and the

SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied.

Table 3. Alarm repeat modes

RPT5

RPT4

RPT3

RPT2

RPT1

Alarm setting

1

1

1

1

1

Once per second

1

1

1

1

0

Once per minute

1

1

1

0

0

Once per hour

1

1

0

0

0

Once per day

1

0

0

0

0

Once per month

0

0

0

0

0

Once per year

VCC

IRQ/FT/OUT/SQW

ABE and AFE Bits

AF Bit in Flags

Register

HIGH-Z

VSO

trec

AI05663