IS25LE128E-RLLA3:P-TY datasheet(150/197 Pages) ISSI

부품명	IS25LE128E-RLLA3:P-TY

상세설명	SERIAL FLASH MEMORY 133/166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

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IS25LE256E/128E

IS25WE256E/128E

Integrated Silicon Solution, Inc.- www.issi.com

150

Rev.A9

03/07/2023

AUTOBOOT REGISTER WRITE OPERATION (WRABR, 15h)

Before the WRABR command can be accepted, a Write Enable (WREN) command must be issued and decoded

by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The WRABR command is entered by shifting the instruction and the data bytes, least significant byte first, most

significant bit of each byte first. The WRABR data is 32bits in length.

CE# must be driven high after the 32nd bit of data has been latched. If not, the WRABR command is not executed.

As soon as CE# is driven high, the WRABR operation is initiated. While the WRABR operation is in progress, Status

IP) bit. The WIP bit is “1” during the WRABR

operation, and is “0” when it is completed. When the WRABR cycle is completed, the WEL is set to “0”.

Figure 8.105 WRABR Sequence In SPI Mode

Instruction = 15h

CE #

SCK

Data In 1

Mode 3

Mode 0

High Impedance

...

Figure 8.106 WRABR Sequence In QPI Mode

15h

Mode 3

Mode 0

7:4

3:0

CE#

SCK

IO[3:0]

Data In 1

...

IS25LE128E-RLLA3:P-TY 데이터시트(PDF) 150 Page - Integrated Silicon Solution, Inc